
    412 F. 2d 255; 162 USPQ 233
    In Re David J. Carlson
    (No. 8164)
    United States Court of Customs and Patent Appeals,
    July 3, 1969
    
      Charles I. Brodsky, attorney of record, for appellnat. A. Russinoff, E. M. Whit-acre, of counsel.
    
      Joseph Schimmel for the Commissioner of Patents. Jere W. Sears, of counsel.
    [Oral argument May 5, 1969 by Mr. Whitacre and Mr. Sears]
    Before Rich, Acting Chief Judge, Holtzoff and McLaughlin, Judges, sitting by designation, Almond and Baldwin, Associate Judges.
    
   Baldwin, Judge,

delivered the opinion of tRe court:

This appeal is from the Patent Office Board of Appeals decision affirming; the examiner’s rejection of claims 4 and 23 in appellant’s application on the ground of double patenting for failing to patent-ably distinguish over the claims of the copending application of Hof-stein, assigned to the assignee of the instant application. Claims 6, 9-19, 22, and 24 have been allowed.

The Invention

The invention relates to electrical circuitry involving an insulated gate, field-effect semiconductor. As background, a semiconductor of this general type usually includes a substrate of doped semiconductor material. Majority carriers may be caused to flow along a channel from a source contact to a drain contact on the substrate in response to an applied bias potential. A gate electrode adjacent to and insulated from the channel may have a varying potential applied thereto relative to the source to modulate the flow of majority carriers along the channel, thus providing an amplifying action.

In the particular construction of appellant’s device, illustrated in Figure 2, the substrate Í2 of lightly doped silicon is provided with source and drain regions S and D containing diffused N type impurities. The interfaces between the source region and the substrate and between the drain region and the substrate may constitute internal rectifying junctions within the device. The gate electrode 22, overlying the channel C along which charge carriers flow from source to drain, is insulated from the channel by a layer of oxide 28. The gate electrode is offset toward the source and away from the drain. Of particular interest is a connection to the substrate, shown in Figure 2 as the metal plate 26 having a wire for making a circuit connection.

Circuit applications for the substrate connection are disclosed in three exemplary amplifying circuits shown in Figures 8, 9 and 10. In each of those circuits, the connection to the substrate cooperates with the internal rectifying junctions previously referred to, in order to achieve a particular circuit operation. However in the absence of disclosure of the internal rectifying junctions, such as for the first three circuits of the application shown in Figures 5, 6 and 7, the specification ascribes no circuit significance to the provision of a connection to the substrate.

The Rejected Claims

Claim 4 is directed to electrical circuitry including an insulated gate field-effect semiconductor, and we have emphasized the portion which appellant asserts patentably distinguishes over the Hofstein claims.

4. In combination:
an insulated gate field effect semiconductor device having a pair of electrodes connected to each other by a conductive channel and being located in spaced relation on a silicon substrate, and a gate electrode insulated from said silicon substrate and located so that the distance between said gate electrode and one of said pair of electrodes is longer than the distance between said gate electrode and the other one of said pair of electrodes, said conductive channel providing a path for current flow between said pair of electrodes in a direction corresponding to the relative polarity of the potential between said electrodes, circuit means for coupling said other one of said pair of electrodes to said substrate of semiconductor material,
an input circuit connected between said gate electrode and said other of said pair of electrodes, and
an output circuit including a d.c. voltage source connected between said pair of electrodes so that said one electrode is biased positively relative to said other electrode whereby said one elctrode oprates as a drain electrode, said other electrode operates as a source electrode and the signal fed back through the inherent capacitance between said gate electrode and said drain electrode is reduced because of the displacement of said gate electrode toward the electrode which operates as a source electrode. [Emphasis added.]

Claim 23 is directed to electrical circuitry including an insulated gate, field-effect semiconductor, not restricted to the offset gate type, and reads:

23. In combination, a semiconductor device including a substrate of semiconductor material having spaced source and drain regions therein, said source and drain regions defining a current path of controllable conductivity, and a gate electrode insulated from said substrate and overlying at least a portion of said current path for controlling the conductivity thereof, and circuit means providing connections to said gate electrode, said source and drain regions and said substrate of semiconductor material. [Emphasis added.]

The Reference

Hofstein discloses that as an improvement on an insulated gate, field-effect semiconductor, the gate electrode may be offset toward the source and away from the drain to reduce the capacitance between the drain and gate electrodes thereby reducing the coupling between the input and output of the device. Other advantages of the offset gate are that the operating frequency of the device is increased and its transconductance is improved. The Hofstein device is provided with electrical circuit connections to the source, gate and drain electrodes only.

Although claim 4 of Hofstein’s application was regarded as exemplary by the examiner for the double patenting rejection, the Hof-stein patent issued without that claim. However, the board on reconsideration indicated that it considered the issues to be the same because of claim 2 of the Hof stein patent, which reads:

2. A field-effect transistor comprising a body of semiconductor material baying a substantially planar surface, a thin layer of insulating material on said surface, a semiconductor channel in said body and extending entirely adjacent and substantially parallel to said surface, a source region adjacent said surface connected to one end of said channel, a drain region adjacent said surface connected to the other end of said channel, said source and said drain regions defining the ends of a charge carrier path through said channel substantially parallel to said surface, and a single continuous gate electrode structure comprising at least one metallic electrode on said insulating layer and opposite a continuous portion of said charge carrier path, one end of said gate electrode structure being closer physically to said source region than the other end of said gate electrode structure is to sáid drain region.

The Rejection

In rejecting the claims on appeal as failing to patentably distinguish from the claims of the commonly assigned Hofstein patent, the examiner set forth his position as to claim 4 as follows:

The remaining difference between the appealed claim 4 and claim 4 of the copending application * * * [is the] ‘’Circuit means for coupling said other one of said pair of electrodes to said substrate of semiconductor material.” * * * [T]his recitation does not patentably distinguish from the connection of the other one of said electrodes to said substrate that is inherent to the electrode being located on the substrate. The phrase “circuit means” calls for no distinctive means in that the structure set forth could be broadly construed as the connection of the electrode to the substrate by whatever manner it is connected, whether it be diffused to the substrate, or formed to the substrate in any manner. “Circuit means,” without more, does not patentably distinguish from the connection of the electrode to the substrate.

As to claim 23, the examiner explained the rejection thus:

The. sole feature structurally distinguishing claim 23 from claim 4 of Serial No. 245,086, is a recitation of “circuit means providing connections to said gate electrode, said source and drain regions and' said substrate of semiconductor material.” It is believed to be abundantly clear that a semiconductor device, to be rendered useful in a circuit, must obviously have means for connecting the device in the circuit. For this reason, the sole differentiating recitation, set forth above, is deemed to be one which does not patentably distinguish the compared claims in that the mere addition of operating connections is an immaterial limitation.

The board affirmed the rejection “for the reasons set forth in the Examiner’s Answer” and adhered to that position on reconsideration.

Opinion

dSTo terminal disclaimer has been filed in this case and, as indicated earlier, the claims are rejected for failure to patentably distinguish over claim 2 of the commonly assigned Hofstein patent.

'Considering claim 23 first, the examiner’s position was that the recitation' in the claim of “circuit means' providing connections to said gate electrode, said source and drain regions and said substrate of semiconductor material” does not patentably distinguish from the Hofstein claim because “the mere addition of operating connections is an immaterial limitation.” We agree that the mere addition of an electrical connection is not of patentable significance in the absence of its prpviding or permitting any different result. Here the different result which appellant’s application disclosed is the connection of the substrate of the semiconductor- device to the two disclosed rectifying junctions between the substrate and the source and drain, respectively, which junctions are represented at 152 and 154 in Figure 8. The application does not disclose that the addition of a connection to a semiconductor device not embodying such junctions would provide any different result. Moreover, claim 23 does not specify the rectifying junctions and appellant does not show that a device as defined in the claim necessarily embodies such junctions. We therefore must conclude that the record before us does not establish that the recitation in claim 28 of circuit means providing a connection to the substrate is a material limitation -which distinguishes patentably from claim 2 of the Hofstein patent and the rejection will therefore be sustained.

As to claim 4, the examiner’s reasoning in rejecting the claim as failing to patentably distinguish over claim 2 of Hofstein was that the allegedly distinguishing “circuit means for' coupling said other one of said pair of electrodes to said substrate of semiconductor material” fails to distinguish from the coupling provided inherently by the fact of location of the electrodes on the substrate. Appellant argues that the “circuit means” is additional to the device structure claimed by Hofstein and that the claims read in the light of th& specification make that clear. Thus appellant states:

When thus read in light of the specification, rejected Claim 4 clearly indicates that the. circuit means connection called for does not encompass either a “mere extension of the source element of the copending [Hofstein] claim” or a “source element of two component parts, one of which would provide the described coupling,” as stated by the Board, but something completely different. That the souree-to-substrate circuit connection called for in the specification (and claim) is in addition to the transistor device is clear from the fact that the transistor is separately described in relation to its illustration in Figures 1 and 2. In that description, reference is expressly made to the inherent source-to-substrate connection. [It states .that the transistor includes a source region diffused into the substrate body during the heating process.]
Because the inherent souree-to-substrate connection (i.e., within the device) is described in one place and the external circuit connection between these elements is described elsewhere, the distinction between the two types of connections becomes manifest.

The claim construction, urged by appellant does not appear consistent with the format in which appellant chose to set up claim 4. In that claim defining a combination, three principal paragraphs are provided reciting an “insulated gate field-effect semiconductor device,” an “input circuit” and an “output circuit.” The inclusion of the “circuit means” recitation within the “semiconductor device” paragraph favors an interpretation of the “circuit means” recitation which would encompass the inherent coupling provided by location of “said other one of said pair of electrodes” on the substrate. Moreover, since claims are to be given the broadest reasonable interpretation during the examination of a patent application, the examiner’s construction of the claims is entirely viable. Appellant has not therefore persuaded us of error in the examiner’s position and the rejection of claim 4 is therefore sustained. .

The decision of the board is affirmed.

Rich, Acting Chief Judge,

dissenting.

The majority opinion seems to me contrary to numerous of our double patenting decisions of the past few years. It is remarkable in not citing a single one of them (or any other authority) to support this double-patenting rejection.

There is some confusion as to just what the basis of the rejection is. The board said, in its opinion on reconsideration and in agreement with the examiner, that “claims 4 and 23 [on appeal] do not describe an invention different than that described by claim 4 of S. N. 245,086 [now the Hofstein patent 3,296,508, claim 2 of which is relied on to support the double patenting rejection].” The Patent Office Solicitor, however, told us at oral argument that he disagreed with that statement by the board. The majority accepts the construction that this is an obvious-type double-patenting rejection rather than a same invention type case. The “not patentably distinguishing” language used by the examiner is ambiguous.

On the merits, I agree with appellant that both of the appealed claims call for a substrate connection which is separate and distinct from “the inherent coupling provided by location of ‘said other one of said pair of elecrtodes’ on the substrate.” The majority tacitly admits that this is true with respect to claim 23 — otherwise it would not have been necessary to “affirm” the rejection of this claim on a ground never mentioned or relied on by the examiner, the board, or the solicitor, namely, that claim 23 does not require that there be rectifying junictions between the substrate and the source and drain and that, without such junctions, the substrate connection would sene no purpose. It seems to me that this is not a proper basis for any kind of double-patenting rejection but rather for a rejection of the claim under 35 USC 112 as indefinite, i.e., not “distinctly claiming.” But no such rejection was made.

I believe that so far as double patenting is concerned we have before us a fact situation similar to those we had in In re Heinle, 52 CCPA 1164, 342 F. 2d 1001, 145 USPQ 131 (1965), and In re Allen, 52 CCPA 1315, 343 F. 2d 482, 145 USPQ 147 (1965), and that the decisions in those cases and others like them control. The patent claims a transistor device and the claims on appeal are directed to combinations of circuit means including the transistor. This is clearly not a .same invention situation, as the board said it was; neither is it an obvious variation of what the patent claims — namely, a transistor device.

I would reverse. 
      
       Serial No. 245,055, filed December 17, 1962.
     
      
       Now U.S. Patent 3,296,508, issued Jan. 3, 1967, on serial No. 245,086, filed Dec. 17, 1962.
     
      
       The portion of appellant’s specification describing the operation of the exemplary circuit of Figure 8, includes the following description of the internal rectifying junctions:
      The source and drain regions 8 and D, shown in FIGURE 2, are doped (N+) and the substrate of silicon body is effectively doped N so that a pair of rectifying junctions 152 and 154 are found between the drain and source regions respectively and the substrate. The substrate side of these diodes operates effectively as the anode. * * *
      It is to be understood that the poling of the rectifying junctions 152 and 154 is representative of a transistor of the type described in connection with FIGURES 1 and 2 where the substrate is of P-type material relative to the source and drain electrodes. However, the transistor device can be fabricated where the substrate is of N-type material relative to the source and drain electrodes. In devices of the latter type the rectifying junctions would be oppositely poled such that the anode side of the rectifying junction appears at the source and drain electrodes, and the cathode side of these junctions appears at the substrate electrode. * * *
     
      
       For example, the application discloses use of the fourth, substrate connection to effectuate an automatic gain control function in connection with the exemplary signal receiving amplifier of Figure 8 which is reproduced as follows:
      
        
      
      When an AGC signal from the intermediate frequency amplifier 143, applied through line 214 to the substrate connection Su of a semiconductor amplifier 144 of appellant’s construction in the RF amplifier stage 136, rises to a certain level the gain of the RF stage is reduced as follows :
      When the potential at the terminal S becomes more positive than the bias potential at the source electrode 148, the rectifying junction 154 is rendered conductive, thus increasing the current flow through the resistor 170. However, the relative bias voltage between the gate electrode 147 and the source electrode 148 remains the same because the gate electrode is referred to the source electrode through the resistor 174. When the potential of the terminal S becomes more positive than the potential at the drain electrode 150 [sic 149], then the rectifying junction 152 is rendered conductive. The conduction of the rectifying junction 152 effectively connects the drain electrode 149 to ground for signal frequencies through the rectifying junctions 152 and 154 and the capacitor 172 whereby the gain of the r-f amplifier stage is reduced.
     
      
       Figure 6 discloses a tuned amplifier circuit in which the substrate connection 67 is not shown connected to any other part of the circuit or discussed in the specification. Figure 7 disclosses another amplifier employing two semiconductor devices for which it is disclosed that the substrates of semiconductor material 111 and 113 of semiconductor devices 100 and 102 have terminals 115 and 117 which are unconnected. Figure 5 showing another amplifier does disclose that “The substrate 48 is connected to the source electrode” but does not explain why or what result may be attributed to such connection.
     
      
        We think it clear from the language of the examiner, and a statement in the original decision of the board expressly agreeing with the examiner that the difference between appealed claim 4 and the patent claim “would fail within the ordinary skill of the art,” that the double patenting rejection is of the “obviousness type,” the rationale of which is well established. We consider it no more than harmless error that the board on reconsideration attributed the basis for such rejection to 35 USC 101, whereas this court concluded in its subsequent decision in In re Rogers, 55 CCPA 1092, 1097,fn. 7, 394 F. 2d 566, 157 USPQ 569 (1968), that such a rejection is actually based upon a judicially created doctrine rather than 35 USC 101.
     
      
       Connections to the gate electrode and the source and drain regions are not urged by appellant to be anything but entirely conventional.
     
      
       It seems apparent that the examiner regarded the deficiency in claim 23 to be related to the matter of the rectifying junctions. Thus, in th same action in which he designated the recitation of the connection to the substrate as an “immaterial limitation,” he held allowable a similar claim (claim 24) which reads:
      24. In combination: a field effect transistor having source and drain regions formed on a substrate of semiconductor material with individual electrodes connected to each of said drain and source regions and said substrate, the interface between said drain and source regions and said substrate forming rectifying junctions, the portion of the substrate separating said drain and source regions forming a channel of controllable conductivity, and a gate electrode insulated from said substrate and overlying a portion of said channel for controlling the conductivity thereof, and circuit means providing connections to said gate, source, drain and substrate electrodes.
     